Top 3 Takeaways from Micron Earnings (and 2 bonus)

Top 3 Takeaways/Questions from Micron Earnings ... and two bonus takeaways from a Intel Presentation

• Pricing dropped in Micron FQ4/CQ3: DRAM Prices down 20% after Trendforce and various sell side analysts said price was flat. Now there is some offset in timing but flat and down 20% are in way different directions. There is a reason and data to back what happened to Micron in FQ4 on DRAM pricing. They later stated that pricing was starting to climb on NAND although it dropped 8% in FQ4
• Micron plans very little to no cost reduction in 2020. Repeatedly stated no NAND cost reduction due to conversion to replacement gate. DRAM cost reduction will be less than 10%. DRAM is somewhat expected and not an issue if pricing holds. But no cost reduction on NAND when it is losing money today has some serious implications for Micron in 2020.
• FQ1 earnings will be less the FQ4. This was a surprise to just about everyone who thought we would get a 2H recovery. Why the drop in a historically good quarter? and this is including 3-5c/share earnings impact of NAND accounting change (BTW there is a good reason Micron is changing NAND depreciation)

2 Bonus items: Intel announced NAND and Optane Roadmap
https://www.anandtech.com/show/14903/intel-shares-new-optane-and-3d-nand-roadmap

• Intel announced they will have new Optane DIMM Modules "Barlow Pass" in 2020 for servers. This seems pretty soon for a follow on given the delays and slow adoption of Apache pass DIMMS. However it is important to keep new generations coming and Intel sometimes delays new products so maybe it wont step on Apache Pass toes too soon. We have cost models for 1st and second gen Optane memory media. Rumor is that Barlow Pass uses Apache pass memory chip (unverified)
• Intel announced 144 layer NAND technology with floating gate. Intel and Micron are both going to struggle with their first generation apart..... mainly from a financial point of view. but the fact that Intel is announcing the 1xx layer part for 2020 is good for Intel customers and a welcome surprise for me. I was getting worried Intel would skip the first gen 1xx NAND technology. NAND costs will keep coming down in 2020/2021 ... we have summaries of where each company stands in cost with 96L and 1xx layer.

Lots of new technologies, financial challenges, and we have the macroeconomic challenges too. 2020 will not be a dull year.

Mark Webb

www.mkwventures.com

3D Xpoint Revenue and Bit Output

We presented bit output and revenue projections for 3D Xpoint at Flash Memory Summit this week. See details below











To calculate this, we modeled Fab wafer capacity, factory loading percentage, yields, die size, cost, pricing, etc and how those are projected to change over the next few years.

Charts are below, full presentation is on our website and Flash Memory Summit site. The full details on all of the parameters going into the model are available to clients

GB Output Projections:

3D Xpoint Revenue Projections:

See presentations for more info. Call to set up meeting to discuss monthly updates to 3D XPoint output, revenue, and status on 2nd Generation 3D Xpoint.

Mark Webb
www.mkwventures.com

See ALL Reports at www.mkwventures.com/reports.html

What's the Best Approach to Persistent Memory at FMS

I will be hosting a panel session on "What is the Best Approach to Persistent Memory" at Flash Memory Summit, Thursday at 2:10PM in Room GAMR 2. On the Panel we will have

• Rahul Advani, Netlist, VP Marketing
• Bill Leszinske, Retired Corporate VP from Intel NVM Solutions Group
• Arthur Sainio, Smart Modular, Director Product Marketing
• Pankaj Bishnoi, Everspin, Director of Business Development

We will discuss what the future of Persistent Memory is and what forms it will take. What is the memory, what is the speed, what is the density, how will we access it?

Stop by and bring you tough questions for the panel!

Mark Webb
MKW Ventures Consulting
www.mkwventures.com

Mark Webb, MKW Ventures at FMS 2019

 I will have a number of presentations at Flash Memory Summit this year. I also look forward to meeting with industry leaders and people who want to develop a better understanding of Memory, Storage, Markets, and which technologies will dominate the next 10 years. I will have updated NAND technology roadmaps and the costs for each company for 2018-2022 and update on where China is positioned in  NAND and DRAM technology.

MRAM Developer Day and Preconference Aug 5th

• Persistent Memory Preconference seminar: I will present an overview of persistent memory, applications, changes over the past year and my forecast for revenue over the next 5+ years. Persistent Memory is here and is real today Monday 8:30-Noon. Rm 206
•  MRAM Developer Day: We have a panel of experts presenting what the future of MRAM will be and how we will get there. I like to say that MRAM is a tale of two markets. Embedded and discrete with two sets of success criteria and two sets of challenges Monday 5-6PM Great America Room

Flash Memory Summit Aug 6-8, 2019

•  PMEM-102-1: Persistent Memory Part 2: Software and Applications Tuesday at 3:40. Market overview of Persistent Memory, Markets, revenue and what is needed to achieve the large CAGR that we are predicting. What has changed in the last year and what has not advanced like we hoped
• NEWM-102B-1: Annual Update on Emerging Memory Technologies Tuesday at 4.55. Here I will present a 1 hour presentation on the status of multiple new memories. What the advantages and disadvantages are for each. We have lots of new memories that have made progress, we will show where they stand on the Product Lifecycle for NVM. Some are shipping today with billions in revenue predicted. Some are 5-10 years from being in an actual product that you can buy. Bring your question on every memory technology
• “Chat with Experts Table”  (Tuesday 7PM). I will be hosting the table on 3D XPoint technology. Come ask questions and discuss the breakthrough memory, what is costs, how it is used, how and where it is made and when the competitors will join the fun.
• NEWM-201-1: 3D XPoint: Current Implementations and Future Trends Wednesday at 8:30AM. I will show new applications in the last year, Costs compared to other technologies, Updated revenue forecast, Bit shipments in 2019 and 2020 including Gen 2 Xpoint, Speed, Endurance. Plus address how development will move forward after the Intel/Micron breakup
•  PMEM-302A-1: What’s the Best Approach to Persistent Memory Today…and Tomorrow? Thursday at 2:10. I am hosting this panel session with experts on persistent memory to present what the future looks like and how will it change computing.

Call or text to set up a meeting and review the information 1:1

Mark Webb

www.mkwventures.com

See details on 3D XPoint Optane Technology at FMS August 7th

Intel 3D Xpoint Optane Update at FMS Aug 7th

I will be presenting at Flash Memory Summit on Intel Optane/3D XPoint. Some highlights below

• Intel Revenue updates for Optane today and in the future
• Technology Cost Update for 1^st and 2^nd Gen of technology
• Performance Update of SSDs and DIMMs
• NEW! DIMM adoption and feedback
• NEW! 3D Xpoint Fab Capacity, bit shipments, and wafer output today and in the future.
• NEW! Micron and Intel Competitive position vs other PCM crosspoint arrays and NVM technologies

Session NEWM 201-1 Wednesday Aug 7^th at 8:30AM

Contact me for appointment to discuss additional details in 1:1 meetings.

Mark Webb

www.mkwventures.com

Top 3 Memory Market Predictions (PLUS Bonus)

Top 5 Memory Market Predictions

We are near the end of CQ2 and data is leaking out on the future. Some predictions from MKW Ventures Consulting. Reminder: Information comes from the discussion on these points as there are pages of data and models behind each one.








1) 2H recovery might happen, but the data doesn't seem to show that. It looks like the 2H "recovery" will be described as "it didn't happen due to other issues" and "we are recovering. Earnings stopped dropping". I like to call these "alternative facts". We can discuss when the real recovery will happen and how to monitor it.

2) Inventory at end customers is dropping and will reach normal amounts in 2H. However, supplier inventory and channel inventory still exists. This causes end customers to push inventory levels below target amounts and to drive prices down

3)  NAND/DRAM bit demand will start to grow again in 2H but overall bit growth will be at or below historical levels (CAGR 35% NAND, 15-20% DRAM). This will not get the market to "recovery". Revenue and earnings are still in "trough"

Bonus Prediction: There will be a recover and we can predict the timing. Inventory will go to normal at supplier and below normal at end customer. Then comes and small demand trigger and the shortage... we can discuss when this will happen.

Bonus Prediction 2: China and Trade... companies are changing their supply chain to deal with China tariffs. This will lead to shipment from and through other countries instead of China. However, uncertainty on how these tariffs play out is slowing growth and investment. China attempts to make memory in China with Chinese owned companies will continue to be VERY minor despite hype until at least 2022 ... but non-Chinese companies will continue to have lots of Fab output from China that has no trade restrictions with the US.

Just an opinion! We will have lots more data at Flash Memory Summit

Mark Webb
www.mkwventures.com

Memory Cycling Capability: Sorry, It's Complex.

I addressed this in a couple presentations at Flash Memory Summit but questions on cycling performance have grown based on 3D Xpoint and QLC. I will highlight why “how many times can you cycle it?” is 10x more complicated that most people realize.

Key items on cycling performance (Random thoughts.... there is a lot more detail)

• Cycling specifications are based on the criteria used to define success. Rarely do bits fail “dead”. They usually are slow to program or erase, read disturb easily, can’t hold charge for a long time, etc. A device spec could be 800us program time and 100us read time and data retention of 5 years. If I change that to 1200us program, 200uS, and 1 year retention, I could hypothetically increase the cycling capability from 3000 cycles to 10,000 cycles. And what if I changed data retention to 1 hour ???

• Cycling specs are based on allowed fail rate and die level/system level error correction to deal with it. This is published in detailed bit error rate data (BER).  Basic NAND  allows us to tolerate thousands of  blocks failing to cycle, and millions of bits that sometimes read erratically. I can always increase redundant blocks and add more ECC capability. These “tricks” prevent the end customer from seeing errors. A QLC cell seems less reliable than TLC or MLC but it is possible to make it MORE reliable to the end user with error correction. 
• In addition to all of the error correction, we can adjust for end user fail rates as well. Is 2% AFR (annual fail rate) OK? 0.7%? 0.2%?  Are you willing to pay 2x the price for the 0.2% fail rate?

• Based on the above statistics and BER, the size of the array matters. This is very important when we talk about emerging memory. Without error correction, my test chip (a few bits) for MRAM or ReRAM or 3DXP may cycle 10M times. When I put 64K bits in an array it might last 1M times. A 1Gbit array will last 100K times… and then we get into error correction and fail rates.

• Theory vs Actual. I have seen multiple papers saying that MRAM has infinite endurance or something like 1E12 cycles. But MRAM is a real product now and with that comes real cycling numbers. I don't believe any MRAM product is spec’d with 1E12 cycles. Think 6 order of magnitude less….. best case. There are ways to manage the cycling up and down. The capability starts at 1E12 and then starts to drop when you actually make real devices. This is the problem with universal memory claims because … wait for it … DRAM and SRAM can ACTUALLY last 1E12 cycles in real products. No emerging memory is even close.

• So, If we just take NAND and things we have seen over the years as examples of the above.
• NAND theoretically can cycle 1E12… charge trapping is a non-ideality that I will ignore
• A small array (1K) can cycle >1M times without any fails.
• I can buy a 1Gbit chip today that can cycle >100K times (50nm SLC with ECC).
• Planar TLC can cycle 3K times…. If I allow 1% failure, it last 10K cycles, the average (median) bit in that array lasts >30K cycles.
• If I slow down the program and read timing dramatically, I can make a TLC 3K part last 10K+
• And hypothetically, If I build a QLC SSD with massive redundancy and overprovisioning (think RAID), I can have 10 drive writes per day for 10 years. Looks like 36,500 cycles to end user.. but it is not

What does all this mean? The memory companies (and some SSD companies) know all of this and have details on tradeoff and how to manage them... Sorry, it's complex. Ask the experts how it works in a given application. Asking “how many cycles does that last?” or saying “QLC isn’t good enough” may not be useful

We can discuss specific questions to ask (BER, FIT, AFR, DPM, etc) and compare NAND, DRAM, MRAM, ReRAM, 3DXP in more detail. We published estimated 3DXP cycling performance numbers. Call for more information

next blog, I will answer the question "is Schrodinger's cat dead or alive??". As I tell my kids when we discuss at the dinner table .... "It's complex" 

Mark Webb

www.mkwventures.com