One of our top area of analysis is chip cost for all memory
chips and even SOCs/logic chips. We are adding 64L YMTC chip to our report that
has costs for all NAND memory from each company from 64L to 1xx layers.
High level Summary:
The chips size takes advantage of xstacking with periphery and
array on top of each other. To a first order the chip is similar size to
Microns 64L part. The reason YMTC chose chip bonding is to control logic
processing and performance separate from array processing on separate wafers and then bonding them together. Having array built
on top of the periphery does impact the periphery but Micron and others have
been successful doing just that. YMTC claims to get much better NAND
performance from the Xstacking process.
The down side is that you have two wafers, the cost to bond
them together and the complexity of running a two process system. We will also
see how Xstacking works in 8 die and 16 die packages needed for SSDs.
The cost, when mature, is modeled to be 34% higher than
Microns 64L CMOS under array part. Since YMTC is not shipping volume yet and
the Fab is projected to be less than 10K wafer per month currently, the actual
cost is pretty far from maturity. We have the cost today, and how it will track
over time as it ramps. We also have 128L projected costs for YMTC (and all
other companies). We include die size, wafer costs, wafer yields, die yields,
bonding cost and how these change over time.
We also have the business model on how this is still a win
for Chinese industry, assuming they can ramp production. And how this impact
NAND pricing and markets in the future.
The volume will be very small to start but, assuming the reported
information is correct, we should see Xstacking chips in products in the next
several months.
Mark Webb
